MOS dynamic random access memories (RAMs) have provided the lowest cost semiconductor storage memory yet achievable. Recent research in the area of MOS dynamic RAMs has led to steadily increasing storage cell density and faster access times. However, as the density of storage cells of an MOS array has increased, the size of the individual cells has become progressively smaller and the current discharging capability of individual storage cells with respect to discharging the bit-sense line capacitance has decreased. Efforts have been made to decrease the access times of dynamic MOS memories by providing circuits which sense relatively small voltage changes of the bit-sense lines. Another approach to decreasing access times has been to couple bit-sense lines to circuits which sense the initial discharge of the bit-sense line by a selected storage cell and in response to cut in and aid the selected storage cell in further discharging the bit-sense line. In the abovementioned co-pending patent application a speed-up circuit which accomplishes this function is described. The memory storage array is broken up into sections, each of which shares, an associated bit-sense line. Each bit-sense line is coupled to a speed-up circuit which includes a latch circuit. The output of each speed-up circuit is connected to the same data output circuit.